The present invention relates, in general, to an input circuit and, in particular, to an input circuit capable of holding data without degrading the performance of the input circuit.
Typically, a logic circuit, such as, for example, a transistor-transistor logic (TTL) circuit, includes an input circuit, e.g., an input buffer, as an interface between a data bus and a circuit that receives an input signal from the data bus. An input circuit generally includes two inverters forming a latch, wherein the input of one inverter is coupled to the output of the other inverter. The input of the first inverter is also coupled to the data bus. The latch generates a logic signal at the input of the first inverter and the generated signal represents data that has the same logic value as the input signal. Because of the latch, the signal at the input of the first inverter continues to represent data having the same logic value even after the data bus enters a high impedance state. Therefore, the input circuit has the capability of holding data.
When the input signal at the data bus switches from one logic voltage level to another logic voltage level, the voltage level at the input of the first inverter remains unchanged because of the latch. The interaction between the signals generated by the latch and the data bus degrades the switching speed of the input circuit, thereby degrading the high frequency performance of the input circuit.
In complementary metal oxide semiconductor (CMOS) logic circuits, an inverter in the input circuit comprises a p-channel insulated gate field effect transistor (FET) and an n-channel insulated gate FET. The source electrodes of the p-channel and n-channel FETs are coupled to a high side and ground, respectively, of a voltage supply. The gate electrodes of the two FETs are coupled together and serve as the input of the inverter. The drain electrodes of the two FETs are coupled together and serve as the output of the inverter. When the voltage at the data bus is higher than the supply voltage of the input circuit, a body diode of the p-channel FET in the second inverter becomes forward biased. Thus, a current path is established from the data bus to the voltage supply of the input circuit via the drain, substrate, and source of the p-channel FET in the second inverter. The current flowing from a high voltage data bus to a low voltage supply of the input circuit may damage the voltage supply.
A diode can be inserted between the voltage supply and the source electrode of the p-channel FET in the second inverter or inserted between the drain electrode of the p-channel FET in the second inverter and the output of the second inverter to stop current flowing from the data bus to the voltage supply. The inserted diode is orientated so that the diode is reverse biased when the voltage at the data bus is higher than the supply voltage. In order to minimize the degradation of logic signals generated by the second inverter, the inserted diode is preferably a Schottky diode because of its low forward bias voltage drop. However, inserting a diode in a CMOS circuit requires bipolar-CMOS (BiCMOS) process, which is more complicated and costly than a pure CMOS process.
Accordingly, it would be advantageous to have an input circuit and a method for holding data. It is desirable for the input circuit to be able to protect a voltage supply against a high voltage at the data bus. It is also desirable for the input circuit to operate without sacrificing the speed of data transmission. Furthermore, it would be advantageous for the input circuit to be manufacturable using a simple and cost effective process.